Nvidia system design interview

Round 5 of 7 · 9 questions reported

See the whole loop

Format: Design discussion, often narrow and concrete
They grade: Internals and failure handling more than broad architecture
Heads-up: Reported topics: rate limiter internals, a host heartbeat control plane, telemetry collectors, a cloud outage dashboard, guardrails for LLM-written SQL.

Questions Nvidia asks in this round 9

Design an autonomous-vehicle camera and perception pipelineSystem designDesign the path from a self-driving car's cameras to its perception outputs: capture, synchronization and timestamps across cameras, image processing, model inference on the…
Last asked Sep 2026
Design a metrics monitoring systemSystem designCollect metrics from every host and service, store them as time series, power dashboards over months of data, and alert when thresholds are crossed.
Last asked Jul 2026
Design a text-to-SQL chatbot with access controlAI systemDesign a chatbot that turns questions into SQL over internal data. Make sure users only reach data they are allowed to see, and stop invented tables, unsafe statements and runaway…
Last asked Jul 2026
Design a payment fraud detection systemML designScore every card payment for fraud within tens of milliseconds, balancing blocked fraud against declined good customers, with labels that arrive weeks later.
Last asked Mar 2026
Design TinyURLSystem designTurn long URLs into short links and redirect visitors fast, at billions of redirects a day, with optional custom aliases and expiry.
Last asked Feb 2026
Design a dashboard with two-way data syncSystem designDesign a dashboard whose data is kept in sync in both directions with a source system: changes made in the source show up in the dashboard, and edits made in the dashboard are…
Last asked Feb 2026
Design a rate limiterSystem designDesign a service that limits how many requests each API client can make. It sits in front of every API endpoint at high traffic.
Possibly retired
Signals crossing power and clock domains in an SoCSystem designIn a system-on-chip with several power domains and clock domains, explain how signals safely cross between them: synchronizers for single bits, handshakes or asynchronous FIFOs…
Possibly retired
Design an LLM inference serving platformAI systemDesign the system that serves several large models to many customers with low latency and high GPU utilization.