Deterministic-order parallel reduction in CUDA

Write a parallel reduction on the GPU (for example a sum over a large float array) whose result does not depend on how threads happen to be scheduled: the additions must happen in a fixed order, so the same input always gives bit-identical output. Explain why an ordinary atomic or tree reduction can give different floating-point results from run to run, then design and code a reduction with a guaranteed order, in the spirit of a parallel prefix sum. Discuss its cost compared with an unordered reduction.